1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor device including a vertical surround gate transistor structure and a method of forming the same as well as a data processing system including the semiconductor device.
Priority is claimed on Japanese Patent Application No. 2007-254172, filed Sep. 28, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, there has been progressed high density integration and high performance of a semiconductor device with shrinkage of transistors that are integrated therein. Further shrinkage of a transistor is difficult. Shrinkage of a transistor may needs for further reduction in the gate length L of the transistor, thereby causing remarkable shot channel effects, and making it difficult to control the threshold voltage of the transistor. This may also cause the increase of S-value of the transistor, which needs higher threshold voltage in view of suppressing OFF-current of the transistor. Increase of the threshold voltage of the transistor due to the increase of S-value makes it difficult to realize or implement a semiconductor device that needs to operate at lower voltage. Shallower diffusion regions performing as source and drain may be effective to reduce the short channel effects, but will increase the resistance of the source and drain, thereby decreasing current through the transistor. When the transistor with shallower source and drain diffusion regions is applied to the cell transistor in DRAM, such shallower diffusion regions allows the increase of junction leakage, thereby deteriorating refresh performance of DRAM. Further shrinkage of two-dimensional structure of MOS transistors would be difficult in order to realize further improvement of the performance of the semiconductor device that includes the MOS transistors.
Adoption of the three-dimensional structure for a transistor may be effective to countermeasure the difficulty of furthermore shrinkage of the transistor. Japanese Unexamined Patent Application, First Publication, No. 5-136374 discloses an example of a three dimensional transistor having a vertical surround gate transistor structure. This three dimensional transistor includes a pillar of semiconductor which extends in a direction vertical to the main surface of a semiconductor substrate. The semiconductor pillar provides a channel. In recent years, study for such three dimensional transistors has been progressed for further shrinkage of the transistor.